Abstract
A comparative evaluation of channel hot carrier (CHC) reliability and pursuance of dopingless FET (DL JLFET) and junctionless FET (JLFET) are studied for various dielectrics and compared with conventional dielectric (SiO2) JLFET. The use of dielectrics such as vacuum near the drain and the high-κ (HfO2) near the source in DL JLFET (VacuHDL JLFET) allows better pursuance and reliability against channel hot carrier (CHC) effects. A simulation study has shown that the pursuance of VacuHDL in terms of Ion/Ioff ratio is improved by 4.5, 19.38 and 39.58 times, respectively, in comparison with vacuum based DL, HJL and JL. Similarly, the intrinsic delay of VacuHDL is improved by 9.5%, 56.8% and 58.7%, respectively, in comparison with VacuDL, VacuHJL and VacuJL. Hence, VacuHDL is a potential candidate for digital circuit applications. Further, we have found that vacuum-based HDL and HJL are more immunes against CHC stress and shown that the drain current of vacuHDL and vacuHJL is reduced by 6.9% and 17.5%, respectively, in comparison with conventional dialectic (SiO2) based DL and JL which is 10.4% and 20.5%. Hence, the incorporation of vacuum dielectric towards drain terminal is helpful in reducing CHC induced effect in comparison with conventional dielectric.
Highlights
Charge plasma (CP) based dopingless field effect transistor (DL-junctionless FET (JLFET)) has captivated profound attention in future CMOS technology due to its high fabrication feasibility and enhance current-driving capability [1], [2]
We have found that vacuum-based HDL and HJL are more immunes against channel hot carrier (CHC) stress and shown that the drain current of vacuHDL and vacuHJL is reduced by 6.9 % and 17.5 %, respectively, in comparison with conventional dialectic (SiO2) based DL and JL which is 10.4 % and 20.5 %
The incorporation of vacuum dielectric towards drain terminal is helpful in reducing CHC induced effect in comparison with conventional dielectric
Summary
Charge plasma (CP) based dopingless field effect transistor (DL-JLFET) has captivated profound attention in future CMOS technology due to its high fabrication feasibility and enhance current-driving capability [1], [2]. The combination of high-κ/vacuum dielectric CP based HDL-JLFET exhibits superior performance in terms of higher Ion/Ioff (~ 1× 108) and least intrinsic delay as compared to other vacuumbased devices. Vacuum HDLJLFET is a potential candidate for digital circuit applications and shows better immunity against CHC stress
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