Defect Generation and Severity Comparison of Negative Bias Temperature Stress-Induced Degradation on 90 nm p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Different Oxide Thicknesses

Abstract

The aim of this study is to investigate negative bias temperature (NBT) stress-induced p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET) degradation in 90 nm complementary metal–oxide–semiconductor (CMOS) technology. The study especially focuses on the effects of NBT stress on the pMOSFETs with different oxide thicknesses, such as 16, 31, and 68 Å, and on its degree of severity compared with the degradation induced by drain avalanche hot-carrier (DAHC) stress and channel hot-carrier (CHC) stress at the same biased voltage and temperature. We find that although NBT-induced damage is more serious in devices with a thicker silicon oxynitride (SiON) dielectric, the predicted lifetimes reveal that the pMOSFETs with thinner oxide layers will be more critical in meeting the reliability requirements. Very similar results are also found for the comparison of NBT stress and CHC stress, i.e., although CHC stress is more severe than NBT stress under the test conditions, NBT stress is more critical under operational conditions, while DAHC stress only causes very minor degradation. Additionally, it is always interesting and important to understand degradation mechanisms. Therefore the gated-diode (GD) method is used in this study to determine the cause of NBT stress-induced degradation. Many insights are found by analyzing the results of the GD measurements and are reported in this work.