Impact of Back-Gate Biasing on the Transport Properties of 22 nm FD-SOI MOSFETs at Cryogenic Temperatures

Abstract

This article reports on the impact of back gate bias on the transport properties and performance of 22 nm fully depleted silicon-on-insulator (FD-SOI) MOSFETs. FD-SOI MOSFETs were analyzed as a function of back-gate bias from 300 down to 8 K in the context of quasi-ballistic transport. Our analysis revealed a significantly larger effect of back-gate bias on effective channel mobility at cryogenic temperatures compared to 300 K. This is attributed to the more significant contribution from surface roughness and Coulomb scattering at low temperatures. In this context, the application of a back-gate bias shifts the position of the charge carriers away from the top gate oxide/semiconductor interface thereby reducing the impact of scattering. These findings are verified with self-consistent calculations of the charge distribution in the FD-SOI structure using a 1-D Schrödinger–Poisson solver. This work provides new insight on the impact of back-gate biasing on apparent mobility, mean free path, and ballistic ratio in FD-SOI MOSFETs at cryogenic temperatures.