Abstract

Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This paper studies the benefits, trade-offs and limitations of aggressive fin width (W) scaling on logic and SRAM device characteristics. TCAD analysis is used to understand the impact of gate length (Lg)scaling along with fin width scaling to optimize AC performance. In this paper, W was scaled from 8nm to 1.6nm. It was found that there is a critical fin width (Wc)at ∼4nm. In the W>Wc region, due to better electrostatics from narrower fin, drain-induced barrier lowering (DIBL), DC performance and SRAM Vt mismatch (Vtmm) were improved. As W was scaled down further to W c ∼ 4nm.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.