Abstract
This paper presents an analytical investigation of the drain current model for symmetric short channel InGaAs gate-all-around (GAA) MOSFETs valid from depletion to strong inversion using a continuous expression. The development of the core model is facilitated by the solution of the quasi-2D Poisson equation in the doped channel, accounting for interface trap defects and fixed oxide charges. Correction to short channel effects such as threshold voltage roll-off, drain induced barrier lowering, and subthreshold slope degradation is later introduced, complemented with channel length modulation, velocity saturation, and mobility degradation from surface roughness, leading to accurate mobile charge density for electrostatic capacitance–voltage and transport characterization. The effect of physical process parameters such as fin width, oxide thickness, and channel length scaling is thoroughly investigated in both on and off states of the transistor. The robustness of the model is reflected by the precise match with published experimental reports in the literature. An Ron of 1160 Ω μm is obtained from output characteristics and a switching efficiency improvement of 2.5 times is estimated by incorporating a high-κ dielectric into the GAA transistor. Numerical 3D simulations from TCAD corroborate the validity of the proposed model in all regions of operation.
Highlights
Electrostatic control in three dimensions has become imperative to reduce the short channel effects (SCEs) in deeply scaled transistors beyond the 22 nm technology node
The degree of SCE affecting threshold voltage (Vth) roll-off, drain induced barrier lowering (DIBL), and subthreshold slope degradation of the short channel transistor can be modeled by the change in this minimum potential obtained from the solution of the quasi-2D Poisson equation written in terms of φ0 under full depletion approximation (FDA) as follows
Channel width, and gate length are scaled toward the deca-nanometer regime, certain nonideal effects come into play and degrade subthreshold characteristics
Summary
Electrostatic control in three dimensions has become imperative to reduce the short channel effects (SCEs) in deeply scaled transistors beyond the 22 nm technology node. Phonon scattering and surface roughness from the wrap-around gate configuration limit the mobility to subpar levels, impeding the performance of silicon nanowires from reaching near ballistic limits This opens room for further improvement in carrier transport by utilizing high mobility III–V semiconductor channel materials. The inherent high mobility of a III–V semiconductor as the active channel material truncates dynamic power dissipation in the transistor, offering the same drive current at a reduced supply voltage.11 This favored InGaAs gate-all-around MOSFETs to gain popularity in switching and logic applications.. An analytical drain current model is proposed for symmetric operation of short channel InGaAs GAA MOSFETs that accurately predicts the carrier density under electrostatic conditions as well as computes drain current from depletion to strong inversion under applied drain bias, incorporating interface traps and volume oxide charges.
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