Abstract
Targeting the sub-45μ domain IMEC is launching two industrial programmes. One is for improved device performance by implementing strained silicon (Si) in the transistor channel for scaled planar MOS devices to improve carrier mobility. Research covers strained Si formation on top of strain relaxed buffer (SRB) layers, silicide formation, shallow junctions, extensions, compatibility, and advanced strain characterisation and device demonstration. IMEC has a production technique for thin SRBs of less than about 200μ. This can be applied selectively to pre-formed isolation structures such as shallow trenches. This is a short news story only. Visit www.three-fives.com for the latest advanced semiconductor industry news.
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