Image processing with high-speed and low-energy approximate arithmetic circuit

Abstract

Nowadays there are plenty of compute-intensive algorithms that are carried out at the edge. Therefore, it is necessary to design low-energy and high-speed circuits. Approximate computing (AC) is an emerging paradigm that can be used in error-resilient applications such as multimedia processing. In this paper, a novel approximate full adder design is proposed with the aim of latency and energy consumption reduction at the cost of producing some errors at the output. The proposed design uses pass transistor and transmission gate logic styles to achieve these aims. The proposed cell and referenced circuits are applied in a vast range of simulation conditions including power supply, ambient temperature, and load variations. Moreover, the constancy of the proposed cell concerning the process variations of carbon nanotubes (CNTs) is studied. All circuits are implemented at the transistor level using carbon nanotube field-effect transistor (CNFET) technology. Experimental results based on HSPICE simulation indicate the superiority of the proposed cell in terms of latency, power-delay product (PDP), and energy-delay product (EDP) criteria against state-of-the-art designs. Moreover, at the application level, image blending is used to study the accuracy metrics such as peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) quantitative metrics. Finally, the PDP, PSNR, and SSIM metrics are simultaneously taken into account as a figure of merit (FOM) to trade-off between circuit and application-level metrics. Quantitative results confirm the better functionality of the proposed approximate full adder cell compared to its counterparts.