Abstract
Full adders are the main block in digital arithmetic. Multipliers, subtractors, and dividers use these blocks as the fundamental part. Approximate computing is a promising method for designing low-power and fast digital circuits, applicable in error resilient applications such as image processing. In this paper, a new current mode logic (CML) approximate full adder proposed. Circuit-level simulation performed by HSPICE applying 32nm Carbon Nanotube Field Effect Transistor (CNTFET) Stanford model. The analysis shows that the proposed circuit's power consumption and delay are highly acceptable, while its error distance (ED) is minimum. The application-level simulation shows that this full adder's peak signal to noise ratio (PSNR) and structural similarity index (SSIM) are the highest among the previous CML approximate full adders.
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