High-Performance and Low-Energy Approximate Full Adder Design for Error-Resilient Image Processing

Abstract

- Full Adder cell is the main building block of larger arithmetic circuits and often is placed along their critical path. Therefore, it is a vital task to design high-performance and low-energy Full Adder cells. In this paper, a novel inexact Full Adder cell is proposed based on carbon nanotube field-effect transistor (CNFET) technology. Comprehensive simulations are carried out at the transistor level by the HSPICE simulator applying the 32nm Stanford library model. The operation of the proposed cell is investigated with different supply voltages, output loads, ambient temperatures, and operating frequencies. At the application level, the proposed cell is applied to the image blending system by MATLAB software. Simulation results confirm that the proposed cell outperforms its counterparts in terms of both transistor and application-level metrics such as delay, power-delay product (PDP), energy-delay product (EDP), peak signal-to-noise ratio (PSNR), and structural similarity (SSIM) index.