III-V/Si dual junction solar cell at scale: Manufacturing cost estimates for step-cell based technology

Abstract

Here, we use a bottom-up approach to estimate the manufacturing costs of GaAsP/Si dual junction (DJ) solar cells, fabricated using step-cell technology. Step-cell features facilitate fast epitaxial lift-off while at the same time can be used to optimize tandem cell performance. The estimated step-cell costs are compared with commercially available GaInP/GaAs/Ge triple junction solar cells. For III-V layers grown on Si, it is assumed that graded Si1-yGey buffer layers are used to manage III-V and Si lattice mismatch. Three different scenarios are considered, basing future estimates on an extensive literature survey. The results show distinct cost benefits of Si based growth versus Ge, mainly due to substrate recycling enabled by epitaxial lift-off of III-V layers. Furthermore, the results indicate that major cost contributors for bonded GaAsP/Si step-cells are metal-organic chemical vapor deposition growth of III-V layers and wafer carrier and bonding, with ∼$9.1/W manufacturing costs for a 30% efficient cell on an 8 in. wafer, under the reference scenario. Under a long-term scenario, this cost is reduced to $1.5/W for a 35% efficient cell. Moreover, with this cost advantage over commercially available monolithic Ge-based multi-junction solar cells, a Si-based DJ step-cell is a likely candidate for a high efficiency low cost energy source, with applications in the areas requiring light-weight power solutions.