Abstract
모바일 WiMAX 표준 IEEE 802.16e의 블록길이 2,304 비트, 부호율 1/2을 지원하는 LDPC(low-density parity-check) 복호기를 설계하였다. 설계된 LDPC 복호기는 최소-합(min-sum) 알고리듬과 layered 복호를 기반으로 <TEX>$96{\times}96$</TEX> 크기의 부행렬을 병렬로 처리하는 부분병렬 구조를 갖는다. 최소-합 알고리듬의 특징을 이용하여 메모리 용량을 감소시킬 수 있는 새로운 방법을 고안하여 적용함으로써 검사노드 메모리 용량을 기존의 방법보다 46% 감소시켰다. Verilog HDL로 설계된 LDPC 복호기를 <TEX>$0.18{\mu}m$</TEX> CMOS 셀 라이브러리로 합성한 결과 174,181개의 게이트와 52,992 비프의 메모리로 구현되었으며, Eb/No=2.1dB의 AWGN 채널에 대해 평균 비트 오율 (BER)는 <TEX>$4.34{\times}10^{-5}$</TEX>이고, 100 MHz@1.8-V로 동작하여 약 417 Mbps의 성능을 갖는다. This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of <TEX>$96{\times}96$</TEX> in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of <TEX>$4.34{\times}10^{-5}$</TEX> for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a <TEX>$0.18{\mu}m$</TEX> CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.
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