Post and pre-layout analysis of Low Density Parity Check (LDPC) decoder using 120nm technology Cadence Encounter Tool

Abstract

Low Density Parity Check (LDPC) codes are the one most powerful error correction codes (ECCs) and approach the Shannon limit[1]. The main advantage of the parity check matrix is the decoder can correct all single-bit errors. A decoding algorithm called Min-Sum (MS) algorithm is used in LDPC decoder. In a MIN-SUM decoding algorithm, check node units (CNU) and variable node units (VNU) are iteratively exchange messages with one another following the rule described by the Tanner graph. Min-Sum decoding is widely used for decoding LDPC codes in many modern digital video broadcasting decoding due to its relative low complexity and robustness against quantization error. In this proposed method, the front-end design flow is done in Verilog and the hardware core is simulated in ModelSim and the performance analysis for various parameters are area (2.153mm2), power(59.035mW)and memory (260.864Megabytes). The Design Rule Check (DRC) is done for back-end design flow by using Cadence Encounter Tool and the comparison results are analysed between the pre-layout and post-layout design flow of LDPC Decoder.