I2C protocol and its clock stretching verification using system verilog and UVM

Abstract

Present day's technology has reached a goal where an entire system can be implemented on a single chip which is nothing but called system on chip (SOC). It involves microcontrollers and various peripheral devices with each peripheral device having its own intellectual property (IP) named as IP cores. Serial Communication is established between these IP cores using various protocols like RS232, RS422 and UART etc. These protocols perform point to point communication which requires huge wiring connections, multiplexing of all the bus connections to deliver the information to the IP Cores. To overcome this I2C protocol is developed by Philips, which is a two line communication. Here only two pins i.e., SCL, SDA establish connection between various devices considering one as master and other as slave, as in [1]. These two pins communicate using particular commands like start, address, read/write, acknowledgement and stop commands. Both 7-bit and 10-bit addressing formats can be used, 10-bit addressing supports more addressing lines i.e., 1024 compared to 127 addressing lines in 7bit mode. Clock stretching case is explained here clearly i.e., when a slave needs to have control on the clock generated by the master. The advantage in this protocol is it has low wiring; data transfer rate can be improved using Ultra-Fast mode (UFm), as in [2]. In this paper they perform verification for the design of an I2C protocol between a master and a slave using system Verilog and UVM in the tool SimVision.