Abstract

This basic concepts and principles of the I2C communication protocol were introduced in this paper. Based on the I2C communication protocol, the eUIDE software platform and the ELAN EM78P259N single-chip microcomputer was used to realize the data transmission and reception between EM78P259N and AT24C02 in assembly language, and the timing relationship diagram of data transmission verification and data transmission SDA and SCL was given. The defects of the existing I2C communication protocol were analyzed, and the improvement schemes were given from the physical layer and the protocol layer, and the advantages and disadvantages between the schemes were evaluated.

Highlights

  • IntroductionKnown as data communication control protocol, aims to ensure the efficiency and reliability of communication between two parties in a data communication network

  • Data communication protocol, known as data communication control protocol, aims to ensure the efficiency and reliability of communication between two parties in a data communication network.The data communication protocol makes a series of conventions for data format, data transmission order and rate, confirmation or rejection, error detection, retransmission control and interrogation

  • This paper mainly introduces the Inter-Integrated Circuit bus communication protocol, and gives the timing diagram and protocol improvement of data transmission verification, data transmission serial SDA and serial SCL

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Summary

Introduction

Known as data communication control protocol, aims to ensure the efficiency and reliability of communication between two parties in a data communication network. When SCL is high again, SDA can't change level, slave receives second bit data, and so on, until reaches stop signal. Each time the host transmits one byte (8 bits), it releases the SDA during the ninth clock pulse and waits for the slave to feed back the acknowledge signal (high/low level of one pulse width). After the host receiving the last byte, a NACK signal is sent to keep synchronized with SCL, the slave is notified to end the data transmission, and the SDA is released, so that the host sends a stop signal. If the master pulls SDA high during the low period before the ninth clock pulse, and ensures that SDA is stable high during high level of SCL, it is considered to be NACK

I2C read and write process
Verification results
I2C communication protocol improvements
Conclusions
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