Abstract
Table lookup is a major process to decide the packet processing throughput and power efficiency of routers. To realize high-throughput and low-power table lookup, recent routers have employed several table lookup approaches, such as TCAM (Ternary Content Addressable Memory) based approach and DRAM (Dynamic Random Access Memory) based approach, depending on the purpose. However, it is difficult to realize both ultrahigh throughput and significant low power due to the trade-off between them. To satisfy both of the demands, this study proposes a hybrid memory design, which combines TCAM, DRAM, PPC (Packet Processing Cache), CMH (Cache Miss Handler), and IP Cache, to enable a high-throughput and low-power table lookup. The simulation results using an in-house cycle-accurate simulator showed that the proposed memory design achieved nearly 1 Tbps throughput with similar power of the DRAM-based approach. When compared to the approach proposed in a recent study, the proposed memory design can realize 1.95x higher throughput with 11% power consumption.
Highlights
A demand for high-throughput and low-power packet processing is becoming serious in routers year by year due to an increase in internet traffic
IP Cache is a supplemental approach of the DRAM- and TCAM-based approaches and accelerates the table lookup with reducing the power consumption [12]–[15]
After a packet is processed using the DRAM or TCAM, the corresponding CMT entry and packets queued in CMQ are released, and the table lookup results are cached into IP Cache and Packet Processing Cache (PPC)
Summary
A demand for high-throughput and low-power packet processing is becoming serious in routers year by year due to an increase in internet traffic. A novel hybrid memory design, which combines the DRAM- and TCAM-based approaches and further adds PPC (packet processing cache), CMH (cache miss handler), and IP Cache, is proposed for high-throughput and low-power table lookup in routers. This study builds an in-house cycle-accurate table lookup simulator which can simulate the proposed memory design and the other conventional table lookup approaches (e.g., the DRAM-based or TCAM-based approaches). This simulator enables to measure the table lookup throughput of a router considering the hardware behavior (e.g., stalling and queuing) while most previous studies evaluated the throughput based on a mathematical analysis using a throughput model without considering the concrete hardware.
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