Hybrid encoding for test data compression

Abstract

Main disputes of digital integrated circuits testing are increasing test data volume and test power. The proposed encoding schemes are a combination of nine coded and selective pattern compression, Alternate Variable Run length code to reduce test data volume. The test cubes are divided into multiples of 8, 16, 32, and 64 blocks to upsurge the relationship among the successive test patterns which offers enriched test data reduction. The test data blocks are encoded with two methods in order to reduce test data volume. In the first method, the test sets are encoded using nine coded with selective pattern coding to expand the test data density. In the second method, the test sets are encoded using nine coded with Alternate variable run length laterally with selective pattern coding to improve the test data compression. Investigational results show that the proposed first and second approaches offer a maximum of 76% and 83% of compression ratio respectively for ISCAS’89 benchmark circuits.