Hybrid ADC based on flash and delay-line structures

Abstract

ABSTRACT A pseudo 9 -bit 10 MSample/s hybrid Analog to D igital Converter (ADC) i s proposed for applying to digital power controller. It features its structure that consists of three 3 -bit ADCs: a flash ADC and two delay -line based window ADCs. The first one works in the entire voltage range. And the other two only work in the desired voltage window to improve the resolution . The ADC is designed and simulated in TSMC 0.35 - m m ixed signal process. Simulation results show that the expected funtions are achieved. Keywords : H ybrid ADC; flash ADC; delay line ; analog delay locked loop (ADL L ) 1. INTRODUCTION Digital controllers show a number of advantages in dc -dc power converters, and thus have received increasing attentions these years [1]. A typical architecture of voltage -mode digital switching power controller is shown in Fig.1. Here an ADC samples the output voltage and provides results to a digital compensator. Then the digitized duty ratio d[n] is calculated. And a d igital pulse width modulator (DPWM) converts d[n] to a time domain signal, d(t). Based on look -up tables inst ea d of multipli ers , the digital compensator implementation has small chip area and low power dissipation [1, 2]. In steady state, the output voltage has little variation from the reference so that the range demanding high resolution is narrowed down to a narrow range aro und the referrence voltage V