Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Seyed Zahrai,Marvin Onabajo

doi:10.3390/jlpea8020012

Abstract

This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6–8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

Highlights

High sampling rate (1–3 GS/s) analog-to-digital converters (ADCs) with medium resolutions (6–10 bits) are utilized in diverse applications, including wireless communication systems [1,2], ultra-wideband (UWB) [3], direct-sampling TV receivers [4,5], and digital oscilloscopes [6]
Hybrid ADC architectures benefit from the combination of several ADCs to achieve high-speed and power-efficient operation
The results indicate that the nonlinearity errors of the hybrid ADC were significantly reduced by the calibration of the flash ADC

Summary

Introduction

High sampling rate (1–3 GS/s) analog-to-digital converters (ADCs) with medium resolutions (6–10 bits) are utilized in diverse applications, including wireless communication systems [1,2], ultra-wideband (UWB) [3], direct-sampling TV receivers [4,5], and digital oscilloscopes [6]. SAR ADCs are usually power-efficient for medium resolutions (6–10 bits) and medium samplings rates (10–200 MS/s), and their digital features benefit from modern CMOS technologies [20,21,22]. Their sampling rate is limited by the need for a high-speed clock for the SAR logic, and by the settling time of the capacitive digital-to-analog converter (DAC) in every cycle. Using subranging or two-step architectures can further reduce the power consumption in ADCs [1,28]

Methods

Results

Conclusion