High-voltage CMOS process for field emission display drivers

Abstract

One challenge of high-voltage CMOS process, which is a very important technology for field emission display(FED) driver IC, is DGO(dual gate oxide) technique. The DGO technique means the integration of both thin and thick gate oxide devices on the same chip. In this paper, one sidewall formation is added in DGO technique; the SEM picture shows that the sidewall can round off the step and guarantee that the second polysilicon can be etched completely. Experimental results show that the breakdown voltage of HV-NMOS and HV-PMOS is 114 V and -140 V, respectively; the level shifter circuit can transfer low-voltage signal(0 V/spl sim/5 V) to high-voltage signal(0 V/spl sim/95 V).