High-Speed Serial–Parallel Multiplier in Quantum-Dot Cellular Automata

Abstract

Quantum-dot cellular automata (QCA) is a nanotechnology-based circuit design technology to design efficient circuits. Serial–parallel multiplier (SPM) is an efficient hardware circuit used in different applications ranging from simple arithmetic circuits, filters to complex cryptographic systems. In this work, an architecture that can be used for realizing SPM in QCA is discussed. Based on that architecture, an efficient 4-bit SPM is implemented in QCA. The proposed multiplier is also realized using efficient shift registers and adders. Parallel and serial shift registers are introduced in the circuit to store the inputs and outputs to increase the reliability of the circuit. The proposed work is the first of its kind to implement SPM with shift registers to store input and output in QCA. The proposed multiplier without shift registers is efficient and at least 66% faster compared to existing designs. The 4-bit multiplier with shift registers has 2271 cells covering an area of 7.74 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {\mathrm{ m}} ^{2}$ </tex-math></inline-formula> with 25.25 clock cycle latency. To showcase, the scalability of a serial adder is also realized using the universal, scalable, and efficient clocking scheme.