Abstract
The Quantum-dot Cellular Automata (QCA) is an up-coming nanotechnology with great prospect to provide compact circuits with low energy compared to CMOS technology. The increasing demand for efficient signal processors necessitates the design of adders and multipliers which are compact and consumes less power. Serial adders are area efficient architectures that can compute n-bit addition with a single adder but takes more time compared to n-bit parallel adders. Serial-parallel multipliers have regular and scalable structures when compared to multipliers that implement more complex multiplication algorithms. This paper proposes an energy and area efficient, 4-bit QCA based serial-parallel multiplier circuit. First QCA based serial adder is designed and then a 2-bit serial-parallel multiplier is realized. This multiplier is scaled-up to form 4-bit serial-parallel multiplier. Design, analysis and simulation of the QCA circuits are performed using QCADesigner- E. Designed circuits are evaluated based on cell count, total area and energy dissipation. It can be inferred from the simulation results that the proposed 4-bit serial-parallel multiplier reduces the cell count, area and energy dissipation compared to reference architectures.
Published Version
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