High-speed low-complexity three-parallel reed-solomon decoder for 6-Gbps mmWave WPAN systems

Abstract

This paper presents a high-speed low-complexity three-parallel Reed-Solomon (RS) decoder for 6-Gbps mmWave WPAN systems. Three-parallel processing is used to achieve 6-Gbps data throughput and low hardware complexity. Three-way parallelizing for syndrome computation and error correction allow the inputs to be received at very high data rates and the outputs to be delivered at correspondingly high rates with a minimum delay. The proposed three-parallel RS decoder has been implemented 90 nm CMOS technology optimized for a 1.2 V supply voltage. The implementation result shows that the proposed RS decoder can operates at a clock frequency of 400 MHz and has a data throughput 9.6-Gbps. The proposed three-parallel RS decoder architecture has a much higher data processing rate and low hardware complexity, and also can be adapted in the FEC devices for mmWave WPAN systems with a data rate of 6 Gbps and beyond.