High-quality NH 3-annealed atomic layer deposited Si-nitride/SiO 2 stack gate dielectrics for sub-100 nm technology generations

Abstract

A novel ultrathin (equivalent oxide thickness, EOT=2.1 nm) atomic layer deposited (ALD) Si-nitride/SiO 2 stack gate dielectrics annealed in NH 3 at a moderate temperature of 550 °C is presented. Metal-oxide-semiconductor (MOS) capacitors are fabricated using the proposed dielectrics. Excellent performances in reduction of leakage currents and electrical stress induced degradations are exhibited by these capacitors. An interesting feature of suppressed soft breakdown events is observed in ramped-voltage-stressing experiments and constant voltage induced time-dependent dielectric breakdown measurements. The dielectrics also exhibited better interface quality, lower bulk trap density, lower trap generation rate and higher reliability in comparison with the ALD Si-nitride/SiO 2 stack dielectrics without NH 3-annealing as well as conventional thermal SiO 2 dielectrics. The proposed stack gate dielectric appears to be very promising for future ULSI devices.