Atomic-layer-deposited silicon-nitride/SiO 2 stack––a highly potential gate dielectrics for advanced CMOS technology

Abstract

An extremely thin (∼2 monolayers) silicon nitride layer has been deposited on thermally grown SiO 2 by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness ( T eq=2.2 nm) efficiently reduce the boron diffusion from p + poly-Si gate without the pile up of nitrogen atoms at the SiO 2/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO 2 especially in the thin (<0.5 nm) thickness region. An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO 2 stack gate dielectrics compared with those of conventional SiO 2 dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO 2 and SiO 2/Si-substrate interfaces for the SiO 2 gate dielectrics and only near the SiO 2/Si-substrate interface for the stack gate dielectrics. Employing annealing in NH 3 at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO 2, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH 3 annealing. Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.