High-performance DDFS design using the equi-section division method

Abstract

In this paper, an equi-section division method utilizing the symmetry property and amplitude approximation of a sinusoidal waveform to design a direct digital frequency synthesizer (DDFS) is proposed. The sinusoidal phase of a one-quarter period is divided into equi-sections. The error value between each line segment value and the sinusoidal amplitude value is stored in a read-only memory (ROM) to reconstruct the real sinusoidal waveform. The upper/lower bound of the maximum error value stored in error-compensation ROM will be derived to determine the minimum required memory wordlength relative to the bit number of the equi-sections. In addition, the minimum size of the total ROMs can be computed according to the bit number of the equi-sections. Thus, the equi-section division method is implemented on a field programmable gate array (FPGA) development board. As a result, the total compression ratio of the DDFS using the equisection division method is superior to that of the DDFS using the traditional compression methods. The simulation and experimental results show that the proposed ROM compression method can effectively achieve a better compression ratio and lower complexity, compared with the DDFS using the traditional compression methods, without affecting the spectrum performance.