A 6-GHz ROM suitable for DDFS application in GaAs HBT technology

Jianwu Chen,Gaopeng Chen,Zhi Jin,Xinyu Liu,Li Wang,Danyu Wu

doi:10.1007/s11434-011-4492-1

Jianwu Chen, Gaopeng Chen + Show 4 more

Open Access

https://doi.org/10.1007/s11434-011-4492-1

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Abstract

Read-only memory (ROM) is widely implemented as a phase-to-amplitude mapping block in direct digital frequency synthesizers (DDFS). This paper derives an equivalent model for the ROM in a DDFS to analyze and reduce the access time that is critical to the performance of the DDFS. Moreover, the signal skew observed in the simulation waveform is illustrated. The proposed 64×3-bit ROM is integrated as a part of an 8-bit DDFS, which operates functionally at 6 GHz. Measurement results demonstrate the improvement in the spur free dynamic range.

Highlights

Read-only memory (ROM) is widely implemented as a phase-to-amplitude mapping block in direct digital frequency synthesizers (DDFS)
Simulation and experimental results, we introduce a 64×3-bit, 6-GHz ROM fabricated using an 1 μm Gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) process for DDFS application
The ROM was fabricated in 1 μm GaAs HBT, with ft and fmax both around 60 GHz

Summary

Introduction

Read-only memory (ROM) is widely implemented as a phase-to-amplitude mapping block in direct digital frequency synthesizers (DDFS). A direct digital synthesizer can be implemented from a phase accumulator, a phaseto-amplitude mapping block, and a digital-to-analog converter. The phase-to-amplitude mapping block is the key to a high performance DDFS. Many architectures and designs for the phase-to-amplitude mapping block in a DDFS have been reported in the literature. The increasing demand for higher speed DDFS circuits and the frequency limitations in CMOS technologies have necessitated the development of DDFSs implemented using heterojunction bipolar transistor (HBT) technology. Gallium arsenide (GaAs) HBT combining high frequency and high yield with a moderate price, shows prominent application in mixed-signal integrated circuits with a high level of complexity, such as the ultrahigh speed DDFS with high spur free dynamic range (SFDR). Simulation and experimental results, we introduce a 64×3-bit, 6-GHz ROM fabricated using an 1 μm GaAs HBT process for DDFS application

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