High-performance 3D-SRAM architecture design

Abstract

A high-performance three-dimension (3D) static random access memory (SRAM) architecture design is presented in this paper. The emerging 3D integration technology involves stacking two or more die connected with a very high density and low latency interface. By using array splitting and bank stacking approaches, the wire length of the proposed 3D SRAM architecture design can be effectively reduced resulting in latency and energy reduction benefits. Performance evaluation results show that about 35.8% latency reduction and 29.4% energy saving can be achieved for a 16MB 4-layer stacked 3D SRAM array. With different sizes of a SRAM array, the proposed 3D architecture has also demonstrated great improvement in latency and energy over the conventional 2D design.