Highly Manufacturable Double-Gate FinFET With Gate-Source/Drain Underlap

Abstract

The speed performance of a double-gate (DG) FinFET CMOS with gate-source/drain (G-S/D) underlap is investigated using 2-D device and mixed-mode circuit simulation. By optimizing the G-S/D underlap, we demonstrate that the fin thickness of a DG FinFET can be significantly increased up to the physical gate length without degrading the speed performance compared to the conventional G-S/D overlap structure, where the fin thickness needs to be less than one-half of the physical gate length to control short-channel effects. Such an increase in fin thickness combined with a relaxed requirement for abruptness in the source/drain profile can dramatically enhance the manufacturability of DG FinFETs for the 32-nm technology node and beyond.