Design Optimization and Performance Projections of Double-Gate FinFETs With Gate–Source/Drain Underlap for SRAM Application

Abstract

Physical device/circuit simulations are used to explore 6T-SRAM cell design and scaling using double-gate (DG) FinFETs with optimized gate-source/drain (G-S/D) underlap. The underlap is designed for the control of threshold voltage (Vt) in the nanoscale FinFET with undoped ultrathin body (UTB). DG FinFETs with underlap are first characterized in terms of for various S/D-extension lengths (Lext), lateral doping-density straggles (sigmaL), and fin-UTB thicknesses (wSi). The relation between and read-static noise margin (SNM) is established to define an optimal SRAM cell, for the Semiconductor Industry Association's International Technology Roadmap for Semiconductors (ITRS) HP45 node with Lg=18 nm, with large SNM as well as large write-0 margin and good immunity to process-induced variations of Lext, sigmaL, wSi, and Lg. Then, a scalability study of the DG FinFET-based SRAM cell is done, showing a continual significant benefit of the optimally designed doable underlaps to the end of the ITRS. In addition to the SRAM application, the novel idea of FinFET Vt control via underlap design is stressed, and its application to high-performance CMOS is discussed.