High-k Materials for Tunnel Barrier Engineering in Floating-Gate Flash Memories

Abstract

Replacing the tunnel oxide or interpoly dielectric of a floating gate Flash memory cell by an engineered tunneling barrier allows lowering the voltage necessary to program or erase the memory cell. We use dual layer dielectric stacks with different dielectric constant, allowing a high tunneling current at relatively low applied voltage while providing good data retention. Stacks consisting of SiO2 with HfO2 or Al2O3 have been studied in single poly memory cells, demonstrating both low voltage programming by tunneling and 10 years of data retention. These stacks have also been integrated as interpoly dielectric (IPD) in a 0.18μm HIMOSTM process for low voltage erasing by tunneling through the IPD.