A simulation study of the effect engineered tunnel barrier to the floating gate flash memory devices

Abstract

Flash memory is a device that is used as a tool to store data electrically. The main advantage of this device is in the non-volatility which can store data without power supply, thus make the device very popular in broad application. Conventional Flash memory generally uses single tunnel oxide with a thickness of 7 nm to 10 nm as a tunnel barrier. In order to obtain good device performance, the thickness of the tunnel barrier must be reduced. If the thickness of the oxide is reduced below than 5 nm, device performance will be better but suffer from problems such as current leakage and data retention. To overcome this problem, a technique identified as Engineered Tunnel Barrier is used to replace the single oxide used in conventional flash memory. The programming characteristic of memories with different tunnel barrier stacks single layer oxide, symmetric layer and asymmetric layer dielectric are investigated using TCAD simulator. The T-suprem-4 was used for device process fabrication and MEDICI simulator used for electrical characteristics. From theoretical, confirmed that the memory with the multilayer tunnel barrier exhibits better programming characteristics in term of, programming tunneling current, programming speed and programming voltage.