Abstract
As the performance of small geometry CMOS improves, sub-0.1 /spl mu/m Si MOSFETs have good RF characteristics, and are expected to replace bipolar and GaAs MESFETs in RF front-end ICs in the near future. However, the parasitic components will be a limiting factor as the device is scaled down to the sub-0.1 /spl mu/m region. In this work, we report a p-channel MOSFET with raised Si/sub 1-x/Ge/sub x/ source/drain (S/D) structure to reduce the parasitic resistance. We find that the selective epitaxial layer can effectively reduce the gate and S/D sheet resistances. In addition, due to the lower Schottky barrier height of the metal/p-Si/sub 1-x/Ge/sub x/ junction, low S/D contact resistivity can be achieved. For gate length L/sub g/=0.5 /spl mu/m, Si/sub 0.86/Ge/sub 0.14/ PMOS exhibits roughly 12% f/sub T/ improvement over the conventional Si PMOS. Moreover, the device with raised Si/sub 0.86/Ge/sub 0.14/ S/D structure produces a 27% improvement in f/sub T/ at a gate length of 0.2 /spl mu/m. This illustrates the importance of maintaining a low series resistance as devices are scaled down.
Published Version
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