(Invited) Cluster-Preforming-Deposited Si-Rich W Silicide: A New Contact Material for Advanced CMOS

Abstract

With recent shrinkage of Si CMOS, the contact resistance at source/drain (S/D) and the external series resistance are becoming determining factors of device performance. Low Schottky barrier height (SBH) at the metal/semiconductor interface is required to reduce the specific contact resistivity. It is well known, however, that for most metallic species, silicide/Si junctions always show a high electron SBH to n-Si owing to the Fermi-level pinning in the range between the mid gap and the valence band edge. This fact imposes a fundamental difficulty for obtaining low contact resistance and high performance in CMOS. Many researchers have already addressed this issue; yet, an unconventional contact material is strongly required. In this work, we demonstrate a novel contact material with low SBH for both n- and p-FET together with excellent diffusion barrier properties: the WSi n (n = 12) composed of W-atom-encapsulated Si n cage clusters.[1] The WSi n film was prepared by the newly developed Cluster-Preforming Deposition (CPD) method.[2] In a hot-wall thermal deposition system, hydrogenated W-atom-encapsulated WSi n H x clusters with well-controlled n values (n ≤ ~12) are preformed by reaction of WF6 and SiH4 in the gas phase. The WSi n H x clusters are then deposited onto a substrate, where they are thermally dehydrogenated and coalesce to the WSi n film with less hydrogen content. The residual fluorine concentration in the film was less than ~0.1 at. % because of the sufficient reduction reaction of WF6 with SiH4 in the gas phase. The formed films have an amorphous structure similar to the hydrogenated amorphous Si, but they are extremely stable against annealing up to 1100 °C.[3] The power formation is entirely suppressed under the CPD condition of very high flow ratio of SiH4/ WF6. We also confirmed that the CPD WSi n exhibits an excellent step coverage over a high-aspect-ratio hole array with 40-nm diameter and 2-μm depth. We evaluated the insertion effect of WSi n film of 5-10 nm thickness into Schottky diodes with high resistivity Si substrates: W/WSi n /n-Si (~2 Ω·cm) and W/WSi n /Ge/p-Si (~5 Ω·cm). The electron SBH in the inserted diodes decreases with n, and in particular, is most reduced to 0.32 eV when n is 12. This indicates that the WSi n film has a Fermi level close to the Si conduction band edge and sufficiently passivates the interfacial states at the Si surface because WSi n is composed of almost Si. This SBH reduction effect is kept even after annealing up to at 700 °C. On the other hand, for the W/WSi n /Ge/p-Si junction, the hole SBH once increases by the insertion but is reduced with annealing temperature, approaching the charge neutrality level close to the valence band edge of Ge, e.g. 0.51 eV with n = 12 after annealing at 600 °C. This property enables the WSi12 film to reduce both the electron and hole SBHs simultaneously in CMOS. Furthermore, the WSi n is a narrow gap semiconductor with a low offset to the band edge of Si or Ge. This band alignment leads to the negligible insertion resistance. To reduce the parasitic series resistance at S/D, it is effective to adopt a thinner barrier film for a low resistance electrode such as Cu. Thus, the barrier properties of the WSi n film against Cu diffusion were investigated using the two test structures: MOS capacitors with a 20-nm thermal oxide and p+-n diodes (junction depth of 100 nm) with and without the WSi n insertion (n = 12, thickness = 5 nm). The WSi n film exhibited excellent diffusion barrier properties for Cu contact; from the TDDB lifetime of the Cu MOS capacitors, the diffusion barrier height was estimated to be 1.33 eV under 5 MV/cm stress and the Cu on Si diodes were stable against annealing up to 600 °C. In conclusion, the insertion of the CPD WSi n (n = 12) film is demonstrated to reduce the electron and hole SBH to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions, while significantly preventing the Cu diffusion with a TDDB barrier height of 1.33 eV under 5 MV/ cm stress. Consequently, this film is a promising contact material for S/D in CMOS. [1] IEDM, 22.5, (2017). [2] J. Chem. Phys., 144, 084703 (2016). [3] J. Appl. Phys., 121, 225308, (2017).