Abstract
This paper reviews our advanced fan-out wafer-level packaging (FOWLP) technologies for hetero-integrated wafer-level system-in-package (WL-SiP) and 3D heterogeneous integration package (3D SWIFT). WL-SiP and 3D SWIFT can integrate various functional dies such as memory, logic, power IC, RF and passive components in wafer-level, therefore are latest fan-out wafer-level packaging technologies for scaled systems with more high performance, multi-functionality, and less power consumption. However, advanced fan-out packaging requires scaled Cu trace pitch and more layers in the redistribution layer (RDL). These trends induce potential reliability challenges. This paper introduces a representative electrical reliability challenge in scaled L/S Cu RDL for advanced fan-out wafer-level packaging (FOWLP).
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