Research on Key Process Technology of RDL-first Fan-out Wafer Level Packaging

Abstract

Traditional fan-out wafer level packaging (FOWLP) technology has lower yields and lower levels of reliability due to RDL delamination, chip offset and wafer warpage. This paper studies a new RDL-first fan-out wafer level packaging technology, which overcomes the challenges of traditional FOWLP technology, and extends FOWLP technology to multi-chip and high I/O counts microsystem packaging application. In RDL-First Fan-out WLP process, RDL manufacturing technology, Wafer Level Molding technology, C2W technology and laser de-bonding technology are the important key technologies. The main materials and key technologies process parameter are optimized and fabricated samples of multi-chip fan-out package with 2 layers RDL of line width/spacing of 10μm/10μm. Multi-chip package samples were passed JEDEC component level test MST L1 & MST L3 and 30 drops of board level drop test.