Suppression strategy for process-induced warpage of novel fan-out wafer level packaging

Abstract

In the study, the novel fan-out wafer level packaging (FOWLP) technology is presented in which the through silicon via (TSV) array interposer layer is manufactured. Compared to conventional FOWLP technology, the present novel FOWLP technology has several advantages of better signal integrity, higher electrical performance, and easier customization. However, similar to the conventional FOWLP technology, the process-induced warpage resulted from the mismatch of the coefficient of thermal expansion (CTE) among the constituent materials is also an essential issue during the fan-out fabrication process, which is notably for successful process integration. This study proposes a comprehensive assessment of the process-induced warpage of the novel FOWLP during the fan-out fabrication process. A process-dependent simulation methodology is introduced, which integrates nonlinear finite element (FE) analysis incorporated with the element death-birth technique. The study starts from establishing a silicon interposer layer with TSV array, attachment of glass carrier, multiple redistribution layers (RDLs), and dielectric layers. The warpage evolution during the fan-out fabrication process is thoroughly evaluated according to the temperature loading profile. To demonstrate the effectiveness of the proposed theoretical model, the novel FOWLP test vehicle is manufactured for experimental measurement. Finally, the parametric study together with response surface methodology is further applied to provide guidelines for suppressing the warpage. Overall, the simulation modeling represents a feasible approach for predicting the process-induced warpage during the fan-out fabrication process.