High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

Abstract

Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. Initially, thinned dies are embedded in a polyimide interposer with a fine-pitch metal fanout, resulting in ultrathin chip packages (UTCPs). Next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by the introduction of an additional layer of interposer, which makes it flat at the chip edge and thus the whole package is named as flat-UTCP. In addition to that, randomness in nonfunctional package positions per panel reduces the overall yield of the whole process up to a certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of four electrically erasable programmable read-only memory dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield.