Abstract
Numerousapplications based on VLSI architectures suffer from large size components that lead to an error at the design stage of floating point arithmetic. Therefore, in the design of a VLSI implementation of FIR filter for various applications such as images increases the design complexity and the time delay effect of the model. This lead tohave difficultyofarchitecturethatincludes the competing requirements like speed, area, and power, application area specialization and knowledge, changing and evolving terms. In this paper, a brief review of VLSI architectures in the field of image processing is depicted such as compression, interpolation, which will be advantageous in order to tackle the issues caused by the complexity in the design and design an optimal architecture with the necessary factors that need to be satisfied.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IOP Conference Series: Materials Science and Engineering
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
