High-speed sub-cycle algorithm for estimation of decaying DC component in current measurements

Abstract

High-speed digital relaying can increase the power system's stability margin and reduce the stress on instruments like transformers, voltage sag duration, and damage from faults. Phasor estimation accuracy plays a crucial role in achieving high-speed digital relaying. However, the fault current measurement obtained from the current transformer usually consists of the Decaying DC Component (DDC). Since the frequency spectrum of DDC is wide, it corrupts the fundamental frequency spectrum. As a result, the phasor estimation of the current measurement is erroneous. Therefore, evaluating the DDC parameters and subtracting from the fault current measurements is necessary to improve the phasor estimation's accuracy. In this paper, a novel sub-cycle-based algorithm is proposed to estimate the DDC parameters. Half-cycle Discrete Fourier Transform (DFT) is used for phasor estimation. The method is tested on synthetic and real-time signals in the Real-Time Digital Simulator (RTDS) and Controller Hardware-In-Loop (CHIL) implemented using the TMS320F28335 microcontroller. A comparison with two previous methods reveals high accuracy and very fast convergence of the proposed method. Also, it detects faults within a sub-cycle duration, making it suitable for high-speed digital relays.