High-speed pull-in of a digital phase-locked loop incorporating an and filter

Abstract

With the rapid progress in high-speed communication, there is increasing demand for a digital phase-locked loop (DPLL) with a faster phase acquisition. This paper proposes a DPLL which uses an AND filter instead of a random walk filter (RWF) as the loop filter. It is verified that the loop can realize a faster phase acquisition without deteriorating the jitter suppression performance. The jitter suppression and phase acquisition performances are analyzed based on the theory of Markov chain, and it is shown that the proposed loop has a wider locking range. Then the phase acquisition speeds of the proposed loop, the conventional binary quantized DPLL, and the DPLL with inserted AND filter are compared for the same jitter suppression. It is seen that the proposed loop can drastically improve the phase acquisition performance for a large initial phase difference. The tendency remains the same even if a noise is added, and the jitter is small. Those properties are verified by a computer simulation with satisfactory agreement with the theoretical analysis.