High speed low power SEU tolerant Pseudo dual port memory in 7nm

Abstract

High density URAM (Ultra Random-Access Memory) in 7nm node is developed as one of the core building blocks for FPGAs (Field Programmable Gate Arrays). It is designed to support columnar architecture of FPGAs. Multiple URAMs are instantiated to form a URAM column. There are multiple URAM columns instantiated over the FPGA. These URAMs are single clocked, two port synchronous memory. URAM is high speed, low power, SEU (Single Event Upset) tolerant pseudo dual port memory. TDM (Time Division Multiplexing) scheme is implemented to achieve two port operation using a single port memory cell. The URAMs are cascadable to enable deeper memory implementation. URAMs have Error Correction Code (ECC) implemented with single bit error correction and double bit error detection capabilities. URAM has power saving features like static power gating, dynamic power gating and auto-sleep mode. URAMs are widely used in 5G deployment and datacenter applications.