SEU mitigation by golay code in the configuration memory of SRAM based FPGAs

Abstract

The susceptibility to Single Event Upset (SEU) is very high for Configuration memory of SRAM based Field Programmable Gate Arrays (FPGA) compared to other FPGA resources. The reduction in feature sizes and core voltages leads to a reduction in the critical charge required to change the state of a memory cell. The SEUs cause failures in the system functionality implemented in FPGA. Fault tolerant techniques have to be adopted for dependable application development of safety systems in FPGAs. The Golay code and the extended Golay code shows better error detection and correction capability than the other error correction codes available for SEU mitigation in the configuration memory of FPGAs. In this paper an error recovery mechanism for configuration memory based on extended Golay code has been proposed. Golay encoder module has been implemented in Spartan-6 FPGA and the encoder module runs at 274.122MHz. This paper also proposes an irradiation experimental setup for validating any of the mitigation techniques against SEUs in the configuration memory of FPGAs.