Abstract
in this paper, a 13-bit hybrid DPWM structure which consists of a second-order Σ-∆ modulator having 6-bit resolution and a counter-comparator block with the 7-bit resolution is designed. The Σ-∆ modulator is based on error feedback concept which increases the effective resolution of DPWM by 6-bit and at the same time reduces clock power requirements and noise disturbances. The timing simulation waveforms of the designed DPWM architecture are verified and PWM pulses of the desirable duty cycle are generated. The Σ-Δ modulator based DPWM is used to drive the power MOSFETs of switching buck converter and Inductor current output voltage waveforms are observed. Ripple quantities of 17.5% and 0.07% are obtained for Inductor current and output voltage which are within the upper limits of 20% and 1% respectively. The steady value of the output voltage obtained is 0.99955V. The result obtained validates the Hybrid DPWM design.
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