High-performance quaternary latch and D-Type flip-flop with selective outputs

Abstract

This paper presents a quaternary latch and two edge-sensitive quaternary flip-flops (QFFs), which are capable of storing a quaternary digit. Two complementary outputs are often generated in a flip-flop inevitably. However, the new designs offer the opportunity to eliminate one of the quaternary outputs with the aim of area and static power reduction. This feature reduces the number of transistors by four and cuts static power dissipation by 47.5% when resistive voltage dividers are used. Simulation results show promising outcomes for the proposed QFFs, which are based on CMOS technology and a single power supply. They provide an excellent compromise between the delay and power factors in comparison with the previous CMOS and CNFET QFFs. The first proposed design with resistive voltage dividers, Design #1, operates with 70.96% and 38.19% lower power-delay product (PDP) than the earlier QFFs with the fastest speed and the lowest power consumption, respectively. The second one with capacitive voltage dividers, Design #2, avoids continuous static current during the production of logic values ‘1’ and ‘2’ and improves PDP even more significantly. Setup time, hold time, critical clock skew, and robustness against process, voltage, and temperature (PVT) variations are also measured showing considerable improvements compared to the previous designs. Finally, the applicability and correct functionality of the proposed QFFs in larger sequential circuits is verified by designing a quaternary shift register and a quaternary decrementing counter.