High performance compact energy efficient error tolerant adders and multipliers for 16-bit image processing applications

Abstract

Compact design is an extremely important criterion in the recent development error tolerant applications based on the high performance processor core. The performance of the processor core depends upon the data processing sub-system architectures. Area, delay and power reduction in the cost of accuracy have become the critical requirement of high quantity data computing Very Large Scale Integration (VLSI) architectures. In this paper, we proposed Compact Energy efficient Error Tolerant Adders (CEETAs) which have efficient design metrics for data intensive applications. To achieve area and energy efficiency, Simplified gate level Approximate Full Adders (SAFAs) are proposed in the inaccurate part of the CEETA and CEETA1 designs. The simulation result shows that the proposed SAFAs based CEETA1 adder exhibits low power consumption, less Power-Delay Product (PDP), less Area-Delay Product (ADP) and it offers a savings of 51.63%, 43.87%, 48.57%, 36.52%, 36.84%, 15.72%, 18.18% area than the conventional CSLA, SAET-CSLA, ETCSLA, HSETA, HSSSA, HPETA-I, HPETA-II, respectively. Further, the Simplified Approximate Full Adders (SAFA1E and SAFA2E), 4-2 Approximate Compressor (AC) modules based High Performance Error Tolerant Multipliers (HPETMs) are proposed for error tolerant applications. To achieve energy and area efficiency with high speed for the high quantity digital data computation, the propagation delay and the gate count reduction on the carry generation path are proposed in the SAFA and AC designs. The proposed HPETM1 has a significant amount of power and area savings and it exhibits 24.95%, 29.87%, 30.41%, 31.79%, 31.68%, 33.87%, and 35.58% lesser delay than the existing AM1, AM2, SSM, ACM1, ACM2, ACM3 and CDM respectively.