Design and Analysis of Approximate Multiplier for Image Processing Application

Abstract

Approximate computing is an emerging technology in digital circuits that improves the accuracy performance in error resilient application. Approximate compressors are the main key element, which is used for the design of approximate multiplier with the efficiency of power and area highly used for the image processing applications. The 4:2 approximate compressors are proposed to reduce the error which produces the output of exact 4:2 compressor. By using the improved compressor, two 4 × 4 multipliers are designed by three different stages of compressor with different accuracies which the errors are reduced by encoding its inputs using generate and propagate signals. The designed 4 × 4 multipliers are used as a building block for scaling up to 16 × 16 and 32 × 32 multipliers. The most accurate multiplier is identified by comparing the results of area, power, delay and power delay product (PDP) and analyzed by mean relative error distance (MRED). In image processing applications, the output image with higher quality and lower power consumption is achieved by the proposed effective multiplier.