High Performance Array Multiplier using Reversible Logic Structure

Abstract

From the past years, research in reversible logic has done very efficiently. It includes synthesis, optimization, simulation and verification. By the reversible structure excessive garbage inputs are eliminated, which in turn the power and speed of the logic design is efficiently utilized. In this paper we are proposed an Array Multiplier which has high performance factors. From recent years the research has going on multipliers to reduce the partial product number. To eliminate this problem we introduced an array multiplier using reversible full adder and reversible half adders. Because every Very Large Scale Integrated (VLSI) circuit designers wants to their circuits should produce less delay and efficient power utilization, because to keep their designs high demands on the market. For this we proposed an array multiplier with reversible half adder and multiplexer based reversible full adder. By this design the combinational path delay and chip area are decreased. Array multiplier is an important design in VLSI because, Multiplication involves key role in Arithmetic and Logical operations. We developed all these designs using Very high speed Hardware Description Language (VHDL) and results are verified through simulation using Xilinx ISE