VHDL Modeling and FPGA based Implementation of a Memory Efficient Huffman Decoder

Abstract

Very High Speed Hardware Description language (VHDL) based modeling of a memory efficient Huffman Decoder using two-bit clustering technique and Field Programmable Gate Array (FPGA) based implementation are presented here. The two-bit clustering technique not only improves memory efficiency but also helps in reducing symbol search time. For an experimental video data with Huffman codes for 32 symbols extended up to 13 bits, the entire memory space is shown to be reduced to a mere 52 words as compared to a normal 213 = 8192 words i.e., an improvement in efficiency from 0.39% to 61.5%. The hardware design and rigorous logic and timing simulation have been carried out with the help of High level design and gate level tools. The technology independent nature of VHDL modeling helps in the realization of the design into any technology. The design and implementation has all the inherent advantages of FPGA and has applications in areas where data compression is desirable such as HDTV etc.