High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology

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This paper demonstrates high performance 35 nm gate length CMOSFETs for 65 nm technology node. The impact of vertical gate scaling on dopant activation in poly-Si gate and device performance is investigated. Total stress controls form both STI and interconnect improved the nMOS drive current up to 5-10% without degradation for pMOS. Excellent controlled 35 nm gate length CMOSFETs are achieved with a high drive current of 650 uA/um for nMOS and 310 uA/um for pMOS at Ioff=70 nA/um at supply voltage of 0.85 V. Low CV/I values of 0.85 ps for nMOS and 1.61 ps for pMOS are obtained. These results are competitive among the latest published data.