Abstract

Noise level frequently set the basic limit on the smallest signal. New noise reduction technology and amplifiers voltage-noise density, yet still offer high speed, high accuracy, and low power solution. Low noise amplifiers always play a significant role in RF technology. Hence in this paper, high linear low noise amplifier (LNA) using cascade self-biased multiple gated transistors (MGTR) is presented. The proposed system is covering 0.9 to 2.4 GHz applications. To verify the functionality of the proposed LNA as a bottleneck of RF technology, a cascade LNA without MGTR is implemented and synthesized. The comparison has been done with the single-gate LNA. From the synthesized result, proposed LNA obtained 10 dBm third-order input intercept point (IIP3) in compare with single-gate LNA at 9dB gain. The proposed LNA is implemented in 90 nm CMOS technology and reported 13 dBm IIP3, 1.9 dB NF and 9 dB gain while consuming 7.9 mW from 2 V supply.

Highlights

  • In the area of RF circuit design, low noise amplifiers (LNAs) are critical blocks

  • Several techniques employed to overcome with nonlinearity and minimized noise figure (NF) in LNAs

  • The results indicate that linearity and power consumption are not efficient

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Summary

INTRODUCTION

In the area of RF circuit design, low noise amplifiers (LNAs) are critical blocks. Several techniques employed to overcome with nonlinearity and minimized noise figure (NF) in LNAs. Bruccoleri in 2004 [3] introduced a feed-forward noisecanceling technique to reduce NF. Kim et al [2] shows the multiple gated transistor (MGTR) method used biasing circuit to remove third-order nonlinearity (second derivative, gm′′ ). They are all using extra circuit for biasing and increase complexity of the design. In the same field, Ding [4] proposed a feed-forward linearization technique. Though efficient linearity performance is achieved, the NF frequency band is not reasonable. For two tone tests, the IIP3 vanishes to 0 dBm. After peer literature study, proposed research work introduces a self-biased MGTR method to enhance the linearity performance of the LNA. A 90 nm CMOS technology is used to implement self-biased MGTR LNA

PROPOSED LNA CIRCUIT BASED ON SELF-BIASING MGTR METHOD
IIP3 of the proposed LNA
Noise Calculation
SIMULATION RESULTS
CONCLUSION
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